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Project Oberon System ported to RISC-V by Rochus Keller

Developer migrates Niklaus Wirth's classic Oberon system from custom RISC-5 to open RISC-V architecture.

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Aug 9

Summary, timeline and people extracted by Claude from 2 items across 2 sources · 9h ago. Quotes are verbatim.

Rochus Keller has ported the Project Oberon System—Niklaus Wirth's complete, documented computer system from 1992—from its original RISC-5 processor to the RISC-V (RV32) instruction set. The migration involved converting from Oberon-07 to Oberon-90 and creating a RISC-V emulator that reproduces Wirth's original memory map, allowing core modules to run unchanged. The project demonstrates that Wirth's design principles of simplicity and regularity transfer well to the open-source RISC-V architecture.

  • Rochus Keller successfully migrated Wirth's Project Oberon System from custom RISC-5 to the open-source RISC-V architecture while preserving original hardware/software contracts.
  • The port maintains compatibility by reproducing Wirth's memory map 1:1, allowing core kernel and I/O modules to run unchanged.
  • RISC-V shares philosophical alignment with Wirth's design—both emphasize regularity and simplicity in instruction set architecture.
  • The project demonstrates that well-documented, modular system design from the 1990s can successfully migrate to modern open architectures.

How it unfolded

  1. Event RISC-V port released on GitHub

    Rochus Keller published a working migration of Project Oberon System to RISC-V (RV32) with modified OP2 compiler backend and VM emulator.

  2. Reaction Community discussion on Hacker News

    Post reached score of 56 with 15 comments on Hacker News, generating technical discussion about the port and RISC-V architecture.

  3. 710 weeks quiet
  4. Event Project Oberon 2013 revision released

    Wirth released an updated version targeting his custom RISC-5 processor, implemented on Xilinx Spartan-3 FPGA, with all code expressible in Oberon.

  5. 1096 weeks quiet
  6. Event Original Project Oberon published

    Niklaus Wirth and Jürg Gutknecht published their complete computer system design including OS, compiler, and language for the NS32032 processor.

What people are saying verbatim

“is now neither available nor is its architecture recommendable”

Niklaus Wirth, System designer · Project Oberon documentation (quoted in HN post) · Dec 31

“in order to extend the desire for simplicity and regularity to the hardware”

Niklaus Wirth, System designer · Project Oberon documentation (quoted in HN post) · Dec 31

“It has been my desire to present the system essentially as it existed 25 years ago, without embellishments”

Niklaus Wirth, System designer · Project Oberon documentation (quoted in HN post) · Dec 31

“the entire hardware/software contract of Project Oberon consists of a memory map plus the instruction set”

Rochus Keller, RISC-V port developer · Hacker News · Aug 8